Inter-integrated circuit interfaces, hereinafter also referred to as I2C interfaces, via which a clock generator device, also referred to as master unit or, master, is able to communicate with multiple slave units in serial manner are available. The master transmits a clock signal by way of a clock line, and a data input signal and a data output signal are transmitted via a bidirectional data line. The data line and the clock line are able to be pulled from a low potential (low level) to a high potential (high level), these potentials corresponding to two logic states. The start of a data transmission and the end of a data transmission, and the data as such are encoded by defined states or state changes on the data line with respect to the state that corresponds to the individual state on the clock line. The change in the logic state occurs instantaneously, but in reality, it is represented by non-vanishing transition times; the transition times differ from component to component and possibly also for the direction of the state change (from low level to high level, or vice versa), because of production tolerances, environmental influences and similar reasons.
Undesired interactions may arise if multiple slave units are connected to an interface. In particular, it may happen that a certain slave unit erroneously interprets a response of another slave unit as a start signal of the master unit, but it may also be the case that other slave units erroneously interpret the response of the particular slave unit as a start signal of the master unit. In conventional I2C interfaces, this problem is eliminated through the use of two delay elements, one delay element being installed on the data input line, and one delay element on the clock line.
However, a disadvantage of this approach is that the parameters of the two delay elements, i.e., the delay times of the transition times, have different effects on the two afore-described problems, so that instead of an optimal solution, no more than a compromise is achievable when using merely two delay elements.
The problem of collisions of a plurality of bus nodes arises when slow slave units are operated at an I2C interface that is operated in normal mode (referred to as standard mode according to the I2C protocol) (100 kHz), in fast mode (according to the I2C protocol) (400 kHz), in expanded fast mode (referred to as fast mode plus (1 MHz) according to the I2C protocol), or in high speed mode according to the I2C protocol) (3.4 MHz). It can be avoided by oversampling if the logic clock of the slave unit is a high-frequency clock (>20 MHz).